1. Field of the Invention
The invention relates to a DRAM arrangement, i.e. a memory cell arrangement with dynamic random access, of the type containing three transistors (3T cell), as well as to a method for making such a cell.
2. Description of the Prior Art
Memory cells known as one-transistor memory cells are currently used in DRAM cell arrangements almost exclusively. A one-transistor memory cell has a readout transistor and a storage capacitor. The information is stored in the storage capacitor in the form of an electrical charge which represents a logical level, 0 or 1. This information can be read out via a word line by controlling the readout transistor via a word line. The electrical charge stored in the storage capacitor drives the bit line.
Since the storage density increases from generation to generation of memory, the required surface area of the one-transistor memory cell must be reduced from generation to generation. This leads to fundamental technological and physical problems. For example, despite a small surface area of the one-transistor memory cell, the storage capacitor must be able to store a minimum amount of electrical charge in order to be able to drive the bit line.
This problem is avoided in an alternative DRAM cell arrangement wherein so-called gain cells are used as storage cells. The information is also stored in such cells in the form of an electrical charge. The electrical charge need not drive a bit line directly, however, but rather is stored in a gate electrode of a transistor, serving only for controlling that transistor, for which purpose a very small amount of electrical charge is sufficient.
A gain cell having three transistors is described by M. Heshami in 1996 IEEE J. of Solid-State Circuits, Vol. 31, no. 3. The electrical charge is stored in a first gate electrode of a first transistor. The storage of the electrical charge occurs with the aid of a second transistor. The first gate electrode is connected to a first source/drain region of the second transistor, and a second source/drain region of the second transistor is connected to the write word line. For storage, a second gate electrode of the second transistor is actuated via a write bit line. The amount of electrical charge and thus the information which is stored in the first gate electrode is determined by a voltage at the write bit line. The readout of the information occurs with the aid of a third transistor. A second source/drain region of the first transistor is connected to a first source/drain region of the third transistor, and a second source/drain region of the third transistor is connected to a read bit line. For the readout a third gate electrode of the third transistor is actuated via a read word line. The amount of electrical charge and thus the information is read out via the read bit line.